code-block-pro / build / shiki / languages / verilog.tmLanguage.json

verilog.tmLanguage.json in Code Block Pro – Beautiful Syntax Highlighting 1.4.0, at build/shiki/languages/verilog.tmLanguage.json

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1	{
2	"fileTypes": ["v", "vh"],
3	"keyEquivalent": "^~V",
4	"name": "verilog",
5	"patterns": [
6	{
7	"include": "#comments"
8	},
9	{
10	"include": "#module_pattern"
11	},
12	{
13	"include": "#keywords"
14	},
15	{
16	"include": "#constants"
17	},
18	{
19	"include": "#strings"
20	},
21	{
22	"include": "#operators"
23	}
24	],
25	"repository": {
26	"comments": {
27	"patterns": [
28	{
29	"begin": "(^[ \\t]+)?(?=//)",
30	"beginCaptures": {
31	"1": {
32	"name": "punctuation.whitespace.comment.leading.verilog"
33	}
34	},
35	"end": "(?!\\G)",
36	"patterns": [
37	{
38	"begin": "//",
39	"beginCaptures": {
40	"0": {
41	"name": "punctuation.definition.comment.verilog"
42	}
43	},
44	"end": "\\n",
45	"name": "comment.line.double-slash.verilog"
46	}
47	]
48	},
49	{
50	"begin": "/\\*",
51	"end": "\\*/",
52	"name": "comment.block.c-style.verilog"
53	}
54	]
55	},
56	"constants": {
57	"patterns": [
58	{
59	"match": "`(?!(celldefine\|endcelldefine\|default_nettype\|define\|undef\|ifdef\|ifndef\|else\|endif\|include\|resetall\|timescale\|unconnected_drive\|nounconnected_drive))[a-z_A-Z][a-zA-Z0-9_$]*",
60	"name": "variable.other.constant.verilog"
61	},
62	{
63	"match": "[0-9]*'[bBoOdDhH][a-fA-F0-9_xXzZ]+\\b",
64	"name": "constant.numeric.sized_integer.verilog"
65	},
66	{
67	"captures": {
68	"1": {
69	"name": "constant.numeric.integer.verilog"
70	},
71	"2": {
72	"name": "punctuation.separator.range.verilog"
73	},
74	"3": {
75	"name": "constant.numeric.integer.verilog"
76	}
77	},
78	"match": "\\b(\\d+)(:)(\\d+)\\b",
79	"name": "meta.block.numeric.range.verilog"
80	},
81	{
82	"match": "\\b\\d[\\d_]*(?i:e\\d+)?\\b",
83	"name": "constant.numeric.integer.verilog"
84	},
85	{
86	"match": "\\b\\d+\\.\\d+(?i:e\\d+)?\\b",
87	"name": "constant.numeric.real.verilog"
88	},
89	{
90	"match": "#\\d+",
91	"name": "constant.numeric.delay.verilog"
92	},
93	{
94	"match": "\\b[01xXzZ]+\\b",
95	"name": "constant.numeric.logic.verilog"
96	}
97	]
98	},
99	"instantiation_patterns": {
100	"patterns": [
101	{
102	"include": "#keywords"
103	},
104	{
105	"begin": "^\\s([a-zA-Z][a-zA-Z0-9_])\\s+([a-zA-Z][a-zA-Z0-9_])(?<!begin\|if)\\s(?=\\(\|$)",
106	"beginCaptures": {
107	"1": {
108	"name": "entity.name.tag.module.reference.verilog"
109	},
110	"2": {
111	"name": "entity.name.tag.module.identifier.verilog"
112	}
113	},
114	"end": ";",
115	"endCaptures": {
116	"0": {
117	"name": "punctuation.terminator.expression.verilog"
118	}
119	},
120	"name": "meta.block.instantiation.parameterless.verilog",
121	"patterns": [
122	{
123	"include": "#comments"
124	},
125	{
126	"include": "#constants"
127	},
128	{
129	"include": "#strings"
130	}
131	]
132	},
133	{
134	"begin": "^\\s([a-zA-Z][a-zA-Z0-9_])\\s(#)(?=\\s\\()",
135	"beginCaptures": {
136	"1": {
137	"name": "entity.name.tag.module.reference.verilog"
138	}
139	},
140	"end": ";",
141	"endCaptures": {
142	"0": {
143	"name": "punctuation.terminator.expression.verilog"
144	}
145	},
146	"name": "meta.block.instantiation.with.parameters.verilog",
147	"patterns": [
148	{
149	"include": "#parenthetical_list"
150	},
151	{
152	"match": "[a-zA-Z][a-zA-Z0-9_]*",
153	"name": "entity.name.tag.module.identifier.verilog"
154	}
155	]
156	}
157	]
158	},
159	"keywords": {
160	"patterns": [
161	{
162	"match": "\\b(always\|and\|assign\|attribute\|begin\|buf\|bufif0\|bufif1\|case[xz]?\|cmos\|deassign\|default\|defparam\|disable\|edge\|else\|end(attribute\|case\|function\|generate\|module\|primitive\|specify\|table\|task)?\|event\|for\|force\|forever\|fork\|function\|generate\|genvar\|highz(01)\|if(none)?\|initial\|inout\|input\|integer\|join\|localparam\|medium\|module\|large\|macromodule\|nand\|negedge\|nmos\|nor\|not\|notif(01)\|or\|output\|parameter\|pmos\|posedge\|primitive\|pull0\|pull1\|pulldown\|pullup\|rcmos\|real\|realtime\|reg\|release\|repeat\|rnmos\|rpmos\|rtran\|rtranif(01)\|scalared\|signed\|small\|specify\|specparam\|strength\|strong0\|strong1\|supply0\|supply1\|table\|task\|time\|tran\|tranif(01)\|tri(01)?\|tri(and\|or\|reg)\|unsigned\|vectored\|wait\|wand\|weak(01)\|while\|wire\|wor\|xnor\|xor)\\b",
163	"name": "keyword.other.verilog"
164	},
165	{
166	"match": "^\\s*`((cell)?define\|default_(decay_time\|nettype\|trireg_strength)\|delay_mode_(path\|unit\|zero)\|ifdef\|ifndef\|include\|end(if\|celldefine)\|else\|(no)?unconnected_drive\|resetall\|timescale\|undef)\\b",
167	"name": "keyword.other.compiler.directive.verilog"
168	},
169	{
170	"match": "\\$(f(open\|close)\|readmem(b\|h)\|timeformat\|printtimescale\|stop\|finish\|(s\|real)?time\|realtobits\|bitstoreal\|rtoi\|itor\|(f)?(display\|write(h\|b)))\\b",
171	"name": "support.function.system.console.tasks.verilog"
172	},
173	{
174	"match": "\\$(random\|dist_(chi_square\|erlang\|exponential\|normal\|poisson\|t\|uniform))\\b",
175	"name": "support.function.system.random_number.tasks.verilog"
176	},
177	{
178	"match": "\\$((a)?sync\\$((n)?and\|(n)or)\\$(array\|plane))\\b",
179	"name": "support.function.system.pld_modeling.tasks.verilog"
180	},
181	{
182	"match": "\\$(q_(initialize\|add\|remove\|full\|exam))\\b",
183	"name": "support.function.system.stochastic.tasks.verilog"
184	},
185	{
186	"match": "\\$(hold\|nochange\|period\|recovery\|setup(hold)?\|skew\|width)\\b",
187	"name": "support.function.system.timing.tasks.verilog"
188	},
189	{
190	"match": "\\$(dump(file\|vars\|off\|on\|all\|limit\|flush))\\b",
191	"name": "support.function.system.vcd.tasks.verilog"
192	},
193	{
194	"match": "\\$(countdrivers\|list\|input\|scope\|showscopes\|(no)?(key\|log)\|reset(_count\|_value)?\|(inc)?save\|restart\|showvars\|getpattern\|sreadmem(b\|h)\|scale)",
195	"name": "support.function.non-standard.tasks.verilog"
196	}
197	]
198	},
199	"module_pattern": {
200	"patterns": [
201	{
202	"begin": "\\b(module)\\s+([a-zA-Z][a-zA-Z0-9_]*)",
203	"beginCaptures": {
204	"1": {
205	"name": "storage.type.module.verilog"
206	},
207	"2": {
208	"name": "entity.name.type.module.verilog"
209	}
210	},
211	"end": "\\bendmodule\\b",
212	"endCaptures": {
213	"0": {
214	"name": "storage.type.module.verilog"
215	}
216	},
217	"name": "meta.block.module.verilog",
218	"patterns": [
219	{
220	"include": "#comments"
221	},
222	{
223	"include": "#keywords"
224	},
225	{
226	"include": "#constants"
227	},
228	{
229	"include": "#strings"
230	},
231	{
232	"include": "#instantiation_patterns"
233	},
234	{
235	"include": "#operators"
236	}
237	]
238	}
239	]
240	},
241	"operators": {
242	"patterns": [
243	{
244	"match": "\\+\|-\|\\*\|/\|%\|(<\|>)=?\|(!\|=)?==?\|!\|&&?\|\\\|\\\|?\|\\^?~\|~\\^?",
245	"name": "keyword.operator.verilog"
246	}
247	]
248	},
249	"parenthetical_list": {
250	"patterns": [
251	{
252	"begin": "\\(",
253	"beginCaptures": {
254	"0": {
255	"name": "punctuation.section.list.verilog"
256	}
257	},
258	"end": "\\)",
259	"endCaptures": {
260	"0": {
261	"name": "punctuation.section.list.verilog"
262	}
263	},
264	"name": "meta.block.parenthetical_list.verilog",
265	"patterns": [
266	{
267	"include": "#parenthetical_list"
268	},
269	{
270	"include": "#comments"
271	},
272	{
273	"include": "#keywords"
274	},
275	{
276	"include": "#constants"
277	},
278	{
279	"include": "#strings"
280	}
281	]
282	}
283	]
284	},
285	"strings": {
286	"patterns": [
287	{
288	"begin": "\"",
289	"end": "\"",
290	"name": "string.quoted.double.verilog",
291	"patterns": [
292	{
293	"match": "\\\\.",
294	"name": "constant.character.escape.verilog"
295	}
296	]
297	}
298	]
299	}
300	},
301	"scopeName": "source.verilog",
302	"uuid": "7F4396B3-A33E-44F0-8502-98CA6C25971F"
303	}
304