code-block-pro / build / shiki / samples / verilog.sample

verilog.sample in Code Block Pro – Beautiful Syntax Highlighting 1.28.0, at build/shiki/samples/verilog.sample

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1	// File : tb_top.sv
2	module tb_top ();
3
4	reg clk;
5	reg resetn;
6	reg d;
7	wire q;
8
9	// Instantiate the design
10	d_ff d_ff0 ( .clk (clk),
11	.resetn (resetn),
12	.d (d),
13	.q (q));
14
15	// Create a clock
16	always #10 clk <= ~clk;
17
18	initial begin
19	resetn <= 0;
20	d <= 0;
21
22	#10 resetn <= 1;
23	#5 d <= 1;
24	#8 d <= 0;
25	#2 d <= 1;
26	#10 d <= 0;
27	end
28	endmodule
29
30	// From https://www.chipverify.com/tutorials/systemverilog
31